Design and implementation of demodulation technique with complex dpll using cordic algorithm
CORDIC (Coordinate Rotation Digital Computer) is a simple and efficient algorithm to calculate hyperbolic and trigonometric functions. It is commonly used when no multiplier hardware is available (e.g., simple micro-controllers and FPGAs). The only operations it requires are addition, subtraction, bit shift and lookup table. The pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase Locked Loop (DPLL) in In-phase and quadrature channel receiver is designed.
The design of CORDIC in the vector rotation mode results in high system throughput due to its pipe-lined architecture where latency is reduced in each of the pipelined stage. For on-chip application, the area reduction in the proposed design can be achieved through optimization in the number of micro rotations. For better loop performance of
first order complex DPLL and to minimize quantization error, the number of iterations are also optimized.
16.A New Approach for High Performance and Efficient Design of CORDIC Processor
This paper presents a new approach for the high performance and hardware efficient design of coordinate rotation digital computer (CORDIC) processor structure. The proposed design approach completely eliminates the ROM requirement of constant arctangent values. Furthermore, efficient designs of carry look ahead adders (CLAs), exploiting one input as constant, in the angle adder/subtractor datapath speeds-up the computation while maintaining regularity. The proposed architecture is implemented in FPGA as well as in 180nm standard cell library. The proposed implementation has about 39% delay improvement in FPGA and about 34% delay improvement in standard cell technology as compared to basic structure. About 47% power savings has been achieved in the proposed structure.
